eMemory’s NeoFuse IP Verified in TSMC 10nm FinFET Process
Hsinchu, Taiwan (Nov. 16, 2016) – eMemory, a leading logic NVM IP provider, today announced the successful demonstration of its security-enhanced NeoFuse IP in TSMC’s 10nm FinFET process, along with IP design kits available to customers for product design-in.
Security concerns associated with high-level chips heighten the need for security functions in logic NVM IP with leading-edge process nodes. eMemory’s security-enhanced NeoFuse IP in TSMC’s 10nm FinFET process includes comprehensive security features to prevent attacks such as fault injection, data tampering and side channel attacks. In addition, a voltage tolerance of over 20 percent for read operations enhances design flexibility and reduces power consumption.
The qualification of NeoFuse IP in TSMC’s 16nm FFC process will be done in early 2017, with completion in 10nm FinFET process following in the second half of 2017. eMemory not only delivers a logic NVM solution in TSMC’s leading edge platforms, but has also developed NeoFuse technology for a wide range of other TSMC process technologies such as ULP, CIS, eFlash, HV, and BCD. eMemory’s NeoFuse technology has been developed in 70 process platforms worldwide, 27 of which have already been verified.
Following eMemory’s successful IP development in a variety of TSMC technology nodes over the past 13 years, eMemory continues its close collaboration with TSMC to extend IP availability to multiple process technologies.
