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Introduction

As the semiconductor industry is prominently marching into the nanometer era, fundamental elements face their physical limits significantly, such as electric field across gate dielectric layers, leakage from an ultra-short channel or steep doping profile, newly incorporated leakage/current models, etc. Therefore, numerous techniques have been adopted and applied to transistors, contacts, backend metal routings, or package techniques. Just looking at the transformation of transistors, it abundant new material, process flows, and techniques are incorporated to meet stringent roadmap requirements, like the gate dielectric layer material and effective thickness, the trench isolation stress, ILD strains, the doping techniques of source/drain extensions, or the porous isolation films on top of them. These changes help the transistors meet target specifications with less variation. However, floating-gate Non-volatile memories (NVM’s), the major category of transistor-based elements, have been affected in many ways. For example, charge retention is no longer favorable with gate dielectric thickness or materials; the thermal budget from complex process flow becomes so tight as not to allow changes, not to mention the reliability models of existing devices leave mere a margin for device operations. These factors make the floating gate NVMs more difficult to incorporate into one existing process and may require more unique process modules and flows to gain acceptable electrical characteristics. As a crucial result, the development of embedded floating-gate NVM technology has been hindered at the 40nm platform and beyond for years.

In the meantime, thanks to thousands of materials, processes, devices, and circuit research and studies over the decades, several alternative categories of memories are surfacing [ref. 1], two of which are even becoming possible for commercial production [ref. 2]. These new categories of memories are resistive RAM (ReRAM or RRAM) and magnetic RAM (MRAM). As few suppliers ship standalone ReRAM products, eMemory, as one of the major NVM IP vendors, has been joining the ReRAM IP development with our design and foundry partners, PSCS (Panasonic Semiconductor Solutions) and UMC for years, and is now releasing its first IP this quarter, Q3 of 2021.

Structure & Process module

A typical ReRAM memory cell has a resistive switching element (RSE) electrically connected to the drain of a transistor. Such RSE, arranged as a backend process module, is composed of transition-metal oxide layers stacked between the top and bottom electrodes and encapsulated by isolation material as a tiny cylinder with just a few nanometers’ diameters. Meanwhile, the top and bottom electrodes further connect upwards and downwards to interconnecting metal layers through short via and buffer layers, respectively, Fig. 1. Such transition-metal oxide stack may contain parts of stoichiometric oxide and non-stoichiometric oxide, which provide RSE with a switching characteristic and will be explained with cell operations later. As the top electrode reaches out to a metal line, the bottom electrode electrically connects downwards to a transistor, creating a 1-transistor 1-ReRAM (1T1R).

A typical ReRAM memory cell has a resistive switching element (RSE) electrically connected to the drain of a transistor. Such RSE, arranged as a backend process module, is composed of transition-metal oxide layers stacked between the top and bottom electrodes and encapsulated by isolation material as a tiny cylinder with just a few nanometers’ diameters. Meanwhile, the top and bottom electrodes further connect upwards and downwards to interconnecting metal layers through short via and buffer layers, respectively, Fig. 1. Such transition-metal oxide stack may contain parts of stoichiometric oxide and non-stoichiometric oxide, which provide RSE with a switching characteristic and will be explained with cell operations later. As the top electrode reaches out to a metal line, the bottom electrode electrically connects downwards to a transistor, creating a 1-transistor 1-ReRAM (1T1R).

Furthermore, the Atomic Layer Deposition (ALD) typically forms the RSE stack. With the virtue of such a relatively low-temperature deposition method, ReRAM rarely requires a built-in thermal budget from its process; and easily becomes embedded into various processes compared to others, especially conventional floating gate devices....More